`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:40:18 04/14/2014 
// Design Name: 
// Module Name:    Vigenere 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Vigenere_enc(
    key,
    data_in,
    data_out,
	 clk
    );
	
	input [127:0] key;
	input [127:0] data_in;
	output [127:0] data_out;
	input clk;
	
	wire [7:0] rom_out_blocks [15:0];
	reg [6:0] address_blocks [15:0];
	wire [7:0] key_blocks [15:0];
	wire [7:0] data_in_blocks [15:0];
	reg [4:0] j = 0;
	wire [7:0] accumulators [15:0];
	
	generate
	genvar i;
		for (i = 0; i < 16; i = i + 1)
		begin: romgen
			ROM_95x8 ROM(
				.addr(address_blocks[i]),
				.data_out(rom_out_blocks[i])
			);
			
			assign key_blocks[i] = key[(i*8)+7:(i*8)];
			assign data_in_blocks[i] = data_in[(i*8)+7:(i*8)];
			//subtract 32 because first printable ASCII is 32 in dec
			assign accumulators[i] = (key_blocks[i] - 32) + (data_in_blocks[i] - 32);
			assign data_out[(i*8)+7:(i*8)] = rom_out_blocks[i];
		end
	endgenerate
	
	always @(posedge clk)
	begin
		for (j = 0; j < 16; j = j + 1)
		begin
			if (accumulators[j] > 94)
				address_blocks[j] <= accumulators[j] - 95;
			else
				address_blocks[j] <= accumulators[j];
		end
	end
	
endmodule
